Regras de codificação em VHDL
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Definição Formal de um Identificador
Os identificadores são nomes que identificam as várias entidades nomeadas do VHDL, tais como objects, procedures, functions, process labels, design entities, etc. Existem duas classes de identificadores: identificadores básicos (basic identifier) e identificadores extendidos (extended identifier).
- Os identificadores básicos podem ser usados para nomear todas as entidades no VHDL.
- Os identificadores extendidos (extended_indentifier) foram incluídos a partir da versão VHDL '93. Esses identificadores são envolvidos com dois caracteres de backslash ("\"), podendo conter qualquer caractere gráfico incluindo espaços e caracteres não ASCII. Também podem incluir palavras reservadas. Neste caso as letras maiúsculas e minusculas são distintas.
A sintaxe dos identificadores é indicada nas regras abaixo. o
- Sintaxe
identifier ::= basic_identifier | extended_identifier
basic_identifier ::= letter { [ underline } letter_or_digit }
letter_or_digit ::= letter | digit
letter ::= upper_case_letter | lower_case_letter
extended_indentifier ::= \graphic_character { graphic_character } \
Regras para o nome de Identificadores Básicos
- Deve consistir apenas de caracteres do conjunto das letras Latinas (a..z), underscores ( _ ) e dígitos (0..9).
- O VHDL é insensitivo ao caso (maiúsculas e minusculas são equivalentes).
- Eles podem ter qualquer comprimento, desde que todo o identificador seja escrito em uma única linha de código.
- O primeiro caractere deve ser uma letra Latina (a..z).
- O underscore não pode ser usado nem como primeiro, nem como último caractere do identificador.
- Não é permitido o uso underscores consecutivos.
- Não é permitido o uso das palavras chave (keywords).
- Não é permitido o uso de caracteres especiais (*, %, $, #, @, \, /, +, -, .).
- Não é permitido o uso letras não latinas (â, ç, ñ, ã, etc.).
- Não é permitido o uso de espaços.
Exemplos
- identificadores legais
basic_identifier:
Decoder_1 FFT Sig_N Not_Ack
extended_indentifier -> legal em VHDL '93
\signal\ \C:\\Cads\ \Signal @#\
Note que o backslash ("\") dentro de um identificador extendido é denotado por dois backslashes ("\\").
- identificadores legais
_Decoder_1 => ERRO: underscore no primeiro caractere 2FFT => ERRO: digito no primeiro caractere Sig_#N => ERRO: caractere especial (#) Not-Ack => ERRO: caractere especial (-)
- identificadores equivalentes
Um_Exemplo_De_Nome um_exemplo_de_nome UM_EXEMPLO_DE_NOME
Palavras reservadas em VHDL
abs -- operator, absolute value of right operand. No () needed.
access -- used to define an access type, pointer
after -- specifies a time after NOW
alias -- create another name for an existing identifier
all -- dereferences what precedes the .all
and -- operator, logical "and" of left and right operands
architecture -- a secondary design unit
array -- used to define an array, vector or matrix
assert -- used to have a program check on itself
attribute -- used to declare attribute functions
begin -- start of a begin end pair
block -- start of a block structure
body -- designates a procedure body rather than declaration
buffer -- a mode of a signal, holds a value
bus -- a mode of a signal, can have multiple drivers
case -- part of a case statement
component -- starts the definition of a component
configuration -- a primary design unit
constant -- declares an identifier to be read only
disconnect -- signal driver condition
downto -- middle of a range 31 downto 0
else -- part of "if" statement, if cond then ... else ... end if;
elsif -- part of "if" statement, if cond then ... elsif cond ...
end -- part of many statements, may be followed by word and id
entity -- a primary design unit
exit -- sequential statement, used in loops
file -- used to declare a file type
for -- start of a for type loop statement
function -- starts declaration and body of a function
generate -- make copies, possibly using a parameter
generic -- introduces generic part of a declaration
guarded -- causes a wait until a signal changes from False to True
if -- used in "if" statements
in -- indicates a parameter in only input, not changed
inout -- indicates a parameter is used and computed in and out
is -- used as a connective in various statements
label -- used in attribute statement as entity specification
library -- context clause, designates a simple library name
linkage -- a mode for a port, used like buffer and inout
loop -- sequential statement, loop ... end loop;
map -- used to map actual parameters, as in port map
mod -- operator, left operand modulo right operand
nand -- operator, "nand" of left and right operands
new -- allocates memory and returns access pointer
next -- sequential statement, used in loops
nor -- operator, "nor" of left and right operands
not -- operator, complement of right operand
null -- sequential statement and a value
of -- used in type declarations, of Real ;
on -- used as a connective in various statements
open -- initial file characteristic
or -- operator, logical "or" of left and right operands
others -- fill in missing, possibly all, data
out -- indicates a parameter is computed and output
package -- a design unit, also package body
port -- interface definition, also port map
procedure -- typical programming procedure
process -- sequential or concurrent code to be executed
range -- used in type definitions, range 1 to 10;
record -- used to define a new record type
register -- signal parameter modifier
reject -- clause in delay mechanism, followed be a time
rem -- operator, remainder of left operand divided by right op
report -- statement and clause in assert statement, string output
return -- statement in procedure or function
select -- used in selected signal assignment statement
severity -- used in assertion and reporting, followed by a severity
signal -- declaration that an object is a signal
subtype -- declaration to restrict an existing type
then -- part of if condition then ...
to -- middle of a range 1 to 10
transport -- signal characteristic
type -- declaration to create a new type
units -- used to define new types of units
until -- used in wait statement
use -- make a package available to this design unit
variable -- declaration that an object is a variable
wait -- sequential statement, also used in case statement
when -- used for choices in case and other statements
while -- kind of loop statement
with -- used in selected signal assignment statement
xor -- operator, exclusive "or" of left and right operands
Além das palavras reservadas originais do VHDL'87, a versão VHDL'93 introduziu novas palavras reservadas:
group -- collection of types that can get an attribute
impure -- an impure function is assumed to have side effects
inertial -- signal characteristic, holds a value
literal -- used in attribute statement as entity specification
postponed -- make process wait for all non postponed process to suspend
pure -- a pure function may not have side effects
rol -- operator, left operand rotated left by right operand
ror -- operator, left operand rotated right by right operand
shared -- used to declare shared objects
sla -- operator, left operand shifted left arithmetic by right op
sll -- operator, left operand shifted left logical by right op
sra -- operator, left operand shifted right arithmetic by right
srl -- operator, left operand shifted right logical by right op
unaffected -- used in signal waveform
xnor -- operator, exclusive "nor" of left and right operands