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__NOTOC__
 
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==Estrutura==
 
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*
 
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*
 
  
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==Código VHDL==
 
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<syntaxhighlight lang=vhdl>
 
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LIBRARY ieee;
 
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USE ieee.std_logic_1164.all;
 
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LIBRARY work;
 
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entity deserial is
 
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GENERIC (bits : INTEGER := 3;  -- Bits do contador interno log2(n)
 
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n : INTEGER := 8 -- Dados seriais transmitidos
 
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);
 
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PORT
 
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(
 
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din :  IN  STD_LOGIC;
 
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inclk0 :  IN  STD_LOGIC;
 
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areset :  IN  STD_LOGIC;
 
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locked :  OUT  STD_LOGIC;
 
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doutS :  OUT  STD_LOGIC;
 
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count_outD :  OUT  STD_LOGIC_VECTOR(bits-1 DOWNTO 0);
 
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count_outS :  OUT  STD_LOGIC_VECTOR(bits-1 DOWNTO 0);
 
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doutD :  OUT  STD_LOGIC_VECTOR(n-1 DOWNTO 0)
 
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);
 
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END entity;
 
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ARCHITECTURE bdf_type OF deserial IS
 
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COMPONENT fast_deserializer
 
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GENERIC (bits : INTEGER; 
 
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n : INTEGER
 
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);
 
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PORT(clk : IN STD_LOGIC;
 
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din : IN STD_LOGIC;
 
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count_out : OUT STD_LOGIC_VECTOR(bits-1 DOWNTO 0);
 
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dout : OUT STD_LOGIC_VECTOR(n-1 DOWNTO 0)
 
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);
 
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END COMPONENT;
 
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COMPONENT fast_serializer
 
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GENERIC (bits : INTEGER; 
 
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n : INTEGER
 
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);
 
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PORT(clk : IN STD_LOGIC;
 
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din : IN STD_LOGIC_VECTOR(n-1 DOWNTO 0);
 
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dout : OUT STD_LOGIC;
 
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count_out : OUT STD_LOGIC_VECTOR(bits-1 DOWNTO 0)
 
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);
 
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END COMPONENT;
 
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COMPONENT altpll0
 
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PORT(inclk0 : IN STD_LOGIC;
 
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areset : IN STD_LOGIC;
 
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c0 : OUT STD_LOGIC;
 
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locked : OUT STD_LOGIC
 
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);
 
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END COMPONENT;
 
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SIGNAL s_clk :  STD_LOGIC;
 
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SIGNAL deserial_data :  STD_LOGIC_VECTOR(n-1 DOWNTO 0);
 
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--Keep
 
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attribute keep: boolean;
 
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attribute keep of deserial_data: signal is true;
 
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BEGIN
 
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doutD <= deserial_data;
 
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deserial_inst : fast_deserializer
 
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GENERIC MAP(bits => bits,
 
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n => n
 
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)
 
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PORT MAP(clk => s_clk,
 
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din => din,
 
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count_out => count_outD,
 
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dout => deserial_data);
 
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serial_inst : fast_serializer
 
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GENERIC MAP(bits => bits,
 
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n => n
 
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)
 
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PORT MAP(clk => s_clk,
 
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din => deserial_data,
 
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dout => doutS,
 
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count_out => count_outS);
 
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pll0_inst : altpll0
 
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PORT MAP(inclk0 => inclk0,
 
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areset => areset,
 
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c0 => s_clk,
 
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locked => locked);
 
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END architecture;
 
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</syntaxhighlight>
 
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==Testbench==
 
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*Código
 
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*Resultado (print)
 
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==Simulações==
 
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{| border="1" cellpadding="5" cellspacing="0" style="text-align: center;"
 
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! colspan="1" style="background: #efefef;" | Nº Bits
 
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! colspan="1" style="background: #efefef;" | ALMs
 
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! colspan="1" style="background: #efefef;" | Delay
 
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! colspan="1" style="background: #efefef;" | Potência (mW)
 
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|-
 
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| x || x || x || x
 
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|-
 
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| x || x || x || x
 
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|-
 
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| x || x || x || x
 
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|-
 
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| x || x || x || x
 
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|-
 
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|}
 

Edição atual tal como às 07h41min de 30 de março de 2016

Disponível em “https://wiki.sj.ifsc.edu.br/index.php?title=Circuito_Deserializador_-_Pedroni_VHDL&oldid=104095”